1. Technical Field
Various embodiments of the inventive concept relate to a semiconductor apparatus, and more particularly, to a semiconductor apparatus having a vertical channel transistor and a method of fabricating the same.
2. Related Art
As an integration degree of semiconductor apparatuses is becoming higher, a two-dimensional area for each unit cell is reduced. With respect to the reduction in the area of the unit cell, various research has been conducted. For example, connection members, such as contact units, for connecting switching devices, bit lines, word lines, and capacitors are fabricated in a buried form.
As part of an effort, vertical channel semiconductor apparatuses are suggested wherein sources and drains of MOS transistors used for switching devices are arranged vertically or three-dimensionally with respect to a substrate surface to induce vertical channels to a substrate.
In vertical channel transistors, the vertical channel is induced by including a pillar pattern perpendicular to a semiconductor substrate, a gate electrode formed on an outer circumference of the pillar pattern, and a source and a drain formed on upper and lower ends of the pillar pattern with the gate electrode therebetween.
The vertical channel transistor is advantageous in that an area of the transistor on the substrate is not increased even when a channel length is increased. However, the manufacturing process of the vertical transistor is very complex since the pillar pattern is formed, and then the gate electrode is formed to surround the outer circumference of the pillar pattern.
More specifically, the vertical channel transistor is manufactured by etching a substrate, in which a pillar is formed, to recess a lower portion of the pillar by a preset width, forming a gate insulating layer on the substrate in which the pillar is formed, depositing a conductive layer for a surrounding gate electrode on the semiconductor substrate in which the gate insulating layer is formed, and spacer-etching the deposited conductive layer to form the surrounding gate electrode surrounding the recessed lower portion of the pillar.
Since the lower portion of the pillar is recessed to form the surrounding gate electrode, a width of the lower portion of the pillar is smaller than that of an upper portion of the pillar, and thus collapse of the pillar pattern occurs.
Further, when the conductive layer deposited to form the surrounding gate electrode is spacer-etched, the conductive layer is not clearly etched, and the pillar patterns are not separated. Therefore, reliability of the semiconductor apparatus may be degraded.